1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device, and more particularly to a step-up write/erase operation.
2. Description of the Related Art
A floating-gate memory cell has been widely used as one of the electrically writable erasable nonvolatile semiconductor memory devices. A floating-gate memory cell has a structure where a floating gate and a control gate are stacked, on a semiconductor substrate. A tunnel oxide film of about 9 nm thick is formed between the semiconductor substrate and the floating gate. An ONO film equivalent to an oxide film of about 14 nm thick is formed between the floating gate and the control gate. The memory cell changes the threshold value of the cell according to the amount of charge accumulated in the floating gate and thereby distinguishes between the state of data “0” (written state) and the state of data “1” (erased state).
In recent years, a MONOS memory cell using a silicon nitride film as a charge accumulation layer in place of a floating gate has been developed. In a MONOS memory cell, a silicon nitride film formed above the semiconductor substrate via a thin tunnel oxide film of about 2 nm is used as a charge accumulation layer. Data is written into or erased from a MONOS cell by injecting electrons or holes from the substrate into the silicon nitride film to change the amount of accumulated charge in the silicon nitride film and thereby changing the threshold value of the memory cell.
When writing and erasing are done repeatedly in a MONOS cell, the interface level increases at the interface between the silicon substrate and the tunnel oxide film as pointed out by S. C. Everist, et al. (reference 1: “Modeling the cycling degradation of silicon-oxide-nitride-oxide-semiconductor transistors,” Appl. Phys. Lett. 60(17)27, April 1992, pp. 2101-2103).
According to reference 1, the increase in the interface level depends on the total amount of charge of the holes passed through the tunnel oxide film. Shin-ichi Minami, et al. have proposed a model where the holes accumulated in the charge accumulation layer pass through the tunnel oxide film when a write voltage is applied, thereby generating an interface level (reference 2: “A Novel MONOS Nonvolatile Memory Device Ensuring 10-Year Data Retention after 107 Erase/Write Cycles,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 11, November 1993, pp. 2011-2017).
According to these references, in order to increase the reliability of a MONOS memory cell, the total amount of charge of the holes passed through the tunnel oxide film and the number of holes accumulated after erasure have only to be decreased. To decrease the total number of holes passing through without changing the number of program and erase cycles, it is suggested that the difference (the threshold voltage window) between the programmed threshold voltage (the threshold voltage after writing) and the erased threshold voltage (the threshold voltage after erasing) have to be made smaller. In addition, to decrease the number of holes after erasure, it is suggested that the threshold value after erasure have to be made more positive.
However, this method has the following problem.
Let a state where electrons are accumulated in the charge accumulation layer be a written state. In this state, when the cell is left at it is for a long time, the accumulated electrons leak gradually into the silicon substrate via the thin tunnel oxide film. As a result, the threshold value of the cell lowers gradually. This might make it impossible to distinguish between the written state and the erased state. When the difference in threshold value between the written state and the erase state is small, the margin for such data collapse becomes small. A similar problem arises in a case where the threshold value of a cell in the erased state increases gradually to the extent that it cannot be distinguished from the written state.
Furthermore, when the erased threshold voltage is made positive and the threshold window is made constant, the written threshold voltage increases. As a result, the amount of negative charge in the charge storage (charge accumulation) electrode in the written state increases further. The increase in the amount of charge in the charge storage electrode makes it easier for the charge to escape from the charge storage electrode through its electric field, which adversely influences the charge retention characteristic.
Therefore, in the prior art, it is difficult to make the increase of the number of program and erase cycles compatible with the securing of a sufficient threshold margin for data collapse. Furthermore, an increase in the interface level when there is no hole accumulation has not been described and measures against the increase have not been disclosed in references 1 and 2.
On the other hand, a step-up writing method where a write voltage of Vpgm is increased gradually has been proposed by G. J. Hemink, et al., as a method of writing data into a conventional floating-gate NAND EEPROM (reference 3: “Fast and accurate programming method for multilevel NAND flash EERPOMS,” VLSI Tech. Dig., pp. 129-130, 1995). In a write operation (“0” program) in a floating-gate memory cell, a high-voltage write pulse Vpgm of about +15V to +25V is applied, with 0V being applied to the well and diffused layer, and a Flowler-Nordheim current (FN tunnel current) is caused to flow thorough the tunnel oxide film, electrons are injected from the channel into the floating gate to charge the floating gate negatively, and the threshold voltage of the memory cell is raised, which completes the write operation.
Using FIGS. 1 and 2, a step-up write operation will be explained. FIG. 2 schematically shows a write voltage pulse waveform applied to the control gate of a memory cell. First, a pulse with a write start voltage of Vpgm0 is applied to the control gage. Thereafter, a verify read operation to verify whether the memory cell has reached a desired threshold voltage is carried out. If the threshold voltage of the cell has not reached the desired one, a write pulse with a voltage obtained by raising the write voltage by a step-up voltage of ΔVpgm is applied to the control gate and the write operation is carried out again. Then, the threshold voltage of the memory cell is verified in a verify operation. Thereafter, a write operation to apply a voltage stepped up in ΔVpgm increments to the control electrode of the memory cell and a verify operation are repeated until the memory cell has exceeded a desired threshold voltage of Vverify.
FIG. 1 shows the change of a drain-current (Id)-gate-voltage (Vg) characteristic of a floating-gate memory cell when writing is done by raising a write pulse voltage of FIG. 2 in ΔVpgm increments and applying the voltage a plurality of times. In FIG. 1, Ith indicates the drain current value of a memory cell producing a threshold voltage. As shown in FIG. 1, in the prior art, the write pulse voltage Vpgm0 is applied to a memory cell with an erased threshold voltage of Vthe, with the result that the threshold voltage of the memory cell rises close to the write threshold voltage significantly. Furthermore, each time a pulse ΔVpgm higher in voltage than the preceding one is applied, the Id-Vg curve shifts in parallel in ΔVth (Pgm) steps toward the high-voltage side. That is, each time a pulse ΔVpgm higher in voltage than the preceding one is applied, the threshold voltage of the memory cell rises in ΔVth (Pgm) steps.
The threshold voltage change ΔVth (pgm) becomes larger, as the step-up voltage ΔVpgm becomes higher. According to a detailed analysis based on “Flash Memory Technical Handbook,” pp. 176-178, 1993, compiled by Fujio Masuoka, it goes as follows. It is assumed that the gate length is LG, the channel width is W, the total capacitance of the floating gate electrode is Ctot, the thickness of the tunnel oxide film is tox, the electric field of the tunnel oxide film at time t is Eox (t), α and β are invariables. It is also assumed that the density of tunnel current satisfies the expression α[Eox(t)]2×exp[−β/Eox(t)] and each write pulse duration is tpgm. It is further assumed that the charge density of a surface depletion layer is QB, the inversion potential is 2φF, the equivalent gate capacitance per unit area measured from the channel is Ceff, the channel potential in programming is Vchannel, and the control gate voltage in programming is VCG. Under these conditions, the dependence Vth(t) of the threshold voltage on the write time when a constant voltage of VCG at t=0 is given by equation (1):Vth(t)=2φF−QB/Ceff+VCG−Vchannel−(Ctot·tox)β/{Cpoly·In[(LGWαβ/Ctot·tox)t+exp[β/Eox(0)]]}  (1)
Here, in a write operation, the channel potential Vchannel can be considered almost constant in the inverted state. Therefore, the difference ΔVpgm in the control gate voltage in writing is equal to the difference ΔVth(pgm) in the increase in the threshold voltage in a specific time within an error of ±10% under the condition that equation (2) holds:tpgm≧6×[(tox·Ctot)/(LGWαβ)]×exp{β/Eox(0)}  (2)
In an ordinary floating-gate memory cell, to hold the control gate voltage in writing low, the coupling ratio C1/Ctot (where C1 is the capacitance between the control gate and the floating gate) is designed to be 0.5 or more. At this time, if the permittivity of the oxide film is ∈ox, the electric field of the tunnel oxide film meets the following expression:(tox·Ctot)/(LGW)∈ox/{1−(C1/Ctot)}≧6.9×10−11[F/m]
Furthermore, in the case of FN tunnel current in a cell using a polycrystalline silicon floating-gate electrode, the following equations are fulfilled:α=3.2×10−6[A/V2], β=2.4×1010[V/m]
Therefore, it follows that, with Eox (0)≧11.5 [Mv/cm], tpgm satisfies equation (2) in the range of a write pulse duration equal to or longer than 6.2×10−6 [s], and that ΔVth (pgm) can be considered almost equal to ΔVpgm in the practical operation range using a write electric field of 11.5 [MV/cm] and a pulse duration of 6.2 μs or longer.
FIG. 3 shows, in more detail, the change of the threshold voltage of a memory cell in fast and slow writing, using the writing method of FIG. 1 is applied. The figure is based on the assumption that a write and erase threshold voltage distribution as shown in FIG. 4 holds. In FIG. 4, it is assumed that the erase threshold voltage has a spread that has Vthel as the lower limit and Vtheh as the upper limit and is broader than the distribution of the write threshold voltage.
In a conventional floating-gate NAND flash memory, the threshold voltage after erasure may be negative. Immediately after erasure, the threshold voltage has a distribution width equal to or greater than 2V. For example, Vthel is set in the range from −4V to −2V and Vtheh is set in the range of from −2V to 0V. In the threshold voltage immediately after writing, the threshold voltage distribution width can be made smaller than the erase threshold voltage width (Vtheh−Vthel) because of a verify operation. Immediately after writing, the threshold voltage is set in the range that has Vverify as the lower limit and Vverify+ΔVth (pgm) as the upper limit.
In FIG. 3, white circles indicate a memory cell with the fastest write speed and black circles indicate a memory cell with the slowest write speed. Here, it is assumed that the cell with the fastest write speed has the upper limit Vtheh of the erase threshold as the initial erase threshold voltage and the cell with the slowest write speed has the lower limit Vthel of the erase threshold voltage as the initial erase threshold. However, even if the initial threshold voltage and the write speed are independent factors, the same reasoning holds because the condition of FIG. 3 is the worst one that will probably happen.
Traditionally, to reduce the number of write pulses and shorten the write time, Vpgm is set so as to be higher than the lower limit Vthw of the write threshold voltage in the memory cell with the fastest write speed. It is preferable that Vpgm be set so as to be in the range that has Vverify as the lower limit and Vverify+ΔVth (pgm) as the upper limit. Normally, Vverify is set, for example, 0.1 to 1V higher than the minimum setting value Vthw of the write threshold value, because the threshold voltage changes with time due to variations in the charge retention characteristic.
On the other hand, in the memory cell with the slowest write speed in FIG. 3, a first write pulse has a threshold voltage smaller than Vverify and a further write operation is carried out. Thereafter, the application of step-up pulses raises the threshold value of the memory cell in ΔVth (pgm) increments each time the number of write pulses increases. After a third write pulse is applied, the threshold voltage of the memory cell is a little lower than Vverify. Consequently, it is determined that the writing is insufficient and a fourth write operation is carried out, with the result that the threshold voltage of the memory cell rises by ΔVth (pgm). This completes the write operation.
Even in the memory cell with the slowest write speed, immediately after the verify write operation, the threshold voltage is in the range that has Vverify as the lower limit and Vverify+ΔVth (pgm) as the upper limit. Although not shown in FIG. 3, even in memory cells with other write speeds, vpgm is in the range that has Vverify as the lower limit and Verify+ΔVth (pgm) as the upper limit immediately after the verify write operation, with the result that Vpgm has a threshold distribution as shown in FIG. 4.
As seen from FIG. 3 and the above explanation, when ΔVpgm is made smaller to narrow the threshold distribution width, the number of pulses necessary for writing increases, depending on the number obtained by raising (Vtheh−Vthel)/ΔVpgm to an integer. This results in an increase in the write time.
In such a step-up write operation, as the step-up voltage ΔVpgm is made higher, the number of pulses necessary for writing decreases, which enables a higher-speed write operation. On the other hand, since the increment ΔVth(pgm) of the threshold voltage of the cell written into becomes almost equal to ΔVpgm, making ΔVpgm larger results in an increase in the threshold distribution width.
Furthermore, consider a case where Vpgm is set so as to be higher than the lower limit Vthw of the write threshold voltage in the memory cell with the fastest write speed to shorten the write time by reducing the number of write pulses. In this case, if C1 is the capacitance between the charge accumulation electrode and the control gate electrode and (Vth−VFB) is the threshold voltage with no charge accumulation on the basis of the flat band voltage of the control electrode, the tunnel insulating film electric field when a first pulse is applied to the memory cell with the slowest write speed of FIG. 3 is expressed as equation (3) in the worst case:{(Vpgm0−Vthel)+(Vth−VFB)}×(C1/Ctot)/tox  (3)
That is, in the case of the memory cell with the fastest write memory cell of FIG. 3, a greater electric field than the one expressed by equation (3) is applied. As a result, the stress electric field causes a dielectric breakdown of the tunnel insulating film or an increase in the interface level or in the fixed charge traps, which result in the deterioration of the charge retention characteristic and a shift in the threshold voltage after writing and erasing are done repeatedly. This causes a reliability problem.
Furthermore, in a NAND EEPROM, when the data is read, a read pass voltage Vread is applied to the control gate of the memory cells unselected in reading. The memory cells unselected in reading must be on (conducting), regardless of the data state. Thus, Vread has to be a sufficiently higher voltage than the write threshold voltage. Therefore, when the threshold distribution width ΔVth of the cell written into is large, the pass voltage Vread must also be high.
As the pass voltage Vread gets higher, the threshold value of the memory cell rises due to Vread stress during the read operation, with the result that the cells can change their state from the erased state (or the state with a low threshold voltage) to the written state (or the state with a high threshold voltage). That is, when making ΔVpgm larger increases ΔVth, it is necessary to raise Vread, which decreases the reliability of the memory cells.
Moreover, in cells written into too high threshold voltage, the number of charges passing through their gate electrode film is large, which causes the problem of degrading the gate insulating film due to repetitive rewrite operations.
For the above reasons, it is difficult to make a high-speed write operation compatible with high reliability (a narrow threshold width). To solve this problem, a method of setting the step-up voltage ΔVpgm to two or more values by switching modes according to the application has been proposed (as disclosed in U.S. Pat. No. 6,031,760 or 6,108,238). With this method, a mode with a large ΔVpgm can be used when the application of memory cells requires a high-speed write operation, whereas a mode with a small ΔVpgm can be used when the application of memory cells requires high reliability (a narrow threshold width).
In this method, however, either the high-speed write operation or the narrow threshold distribution is given priority by mode selection, but both of them cannot be satisfied at the same time.
As described above, with the conventional MONOS cell, it is difficult to make the increase in the number of repeatable rewrite operations compatible with securing a threshold margin for data collapse. Furthermore, in the conventional floating-gate cell step-up writing method, it is not clear how the step-up voltage ΔVpgm is set to make high-speed writing compatible with high reliability (or a narrow threshold distribution). Therefore, a nonvolatile semiconductor memory using a step-up writing method capable of making high-speed writing compatible with high reliability has been needed. In addition, a step-up writing method capable of increasing the number of repeatable rewrite operations without degrading the threshold margin was also needed.